Successive approximation A/D converters are widely used in many applications, because they can be implemented with relatively simple circuitry, have excellent compatibility with CMOS processes, can be manufactured at relatively low cost, and can achieve a relatively fast conversion time. For example, in recent years, advanced electronic control techniques have come to be used to drive motors, and successive approximation A/D converters are used as important component parts in some of such systems.
In applications such as motor control, an A/D converter is used in a feedback loop. Successive approximation A/D converters are suitable for such applications because their latency is relatively small and because there is a direct correspondence between input analog data and output data. Other A/D conversion schemes, such as the delta-sigma scheme, are not suitable for such applications because there is no direct correspondence between input analog data and output data.
Of various types of successive approximation A/D converters, a double-stage type can implement a high-resolution A/D converter with a relatively small chip area. A double-stage successive approximation A/D converter comprises a main DAC which determines high-order bit values and a sub DAC which determines low-order bit values. For the main DAC and sub DAC, a capacitor array or resistor array is used, or they may be used in combination. A successive approximation A/D converter disclosed in an embodiment herein is one that uses a capacitor array for the main DAC and a resistor array for the sub DAC.
FIG. 1 is a diagram showing a circuit example of a 10-bit successive approximation A/D converter that uses a capacitor array for the main DAC and a resistor array for the sub DAC.
The successive approximation A/D converter of FIG. 1 comprises a main DAC (MDAC) which includes a capacitor array of C0′ and C0 to C4 and a switch array of SM0′ and SM0 to SM4, a sub DAC (DSUB) which includes a resistor array of RS0, RS1, . . . , RS31 and a switch array of SS0, SS1, . . . , SS31, a comparator CMP, and a successive approximation control circuit (SAR LOGIC) SAR. The successive approximation A/D converter samples an input voltage Vin and, after determining the values of the high-order five bits using the main DAC, determines the values of the low-order five bits using the sub DAC.
The configuration and operation of the successive approximation A/D converter of FIG. 1 are well known, and therefore a further detailed description thereof will not be given here.
In the successive approximation A/D converter of FIG. 1, the capacitive main DAC has the responsibility of sampling and holding an analog signal as well as the responsibility of performing the A/D conversion of the signal.
In applications to motor control or the like, it may become necessary to simultaneously sample signals from a plurality of channels, that is, to sample the values of a plurality of analog signals at the same time instant, and to convert them into digital form. There are two methods for accomplishing the simultaneous sampling from the plurality of channels: one is a simple method that provides as many A/D converters as there are channels to be sampled (the first method) and the other is a method that provides a single A/D converter and as many sample-and-hold circuits as there are channels to be sampled (the second method).
FIG. 2 is a diagram showing a circuit configuration for performing three-channel simultaneous sampling using the first method. The circuit of FIG. 2 comprises three successive approximation A/D converters ADCA, ADCB, and ADCC, each having the same configuration as that shown in FIG. 1.
Each successive approximation A/D converter takes up a relatively large chip area because the area of the capacitive main DAC is large. Accordingly, the circuit configuration of FIG. 2, which requires the provision of as many A/D converters of relatively large size as there are channels to be sampled, has had the problem that the circuit takes up a large silicon area and the manufacturing cost is high.
FIG. 3 is a diagram showing a circuit configuration for performing three-channel simultaneous sampling using the second method. The circuit of FIG. 3 comprises three sample-and-hold circuits (S/Hs) SHA, SHB, and SHC, a switch SD, and one successive approximation A/D converter ADC which has the same configuration as that shown in FIG. 1.
The circuit configuration of FIG. 3 has only one A/D converter, but requires the provision of as many sample-and-hold circuits as there are channels. Each sample-and-hold circuit uses a capacitive element, but this capacitive element takes up substantially the same area as the capacitive main DAC; accordingly, the circuit configuration of FIG. 3 also has had the problem that the circuit takes up a large silicon area and the manufacturing cost is high.
Further, the sample-and-hold circuits of FIG. 3 each require the use of an amplifier because an electric charge must be supplied to the main DAC when ADC performs sampling. Since this amplifier usually cannot amplify voltages near the power rails, the sample-and-hold circuit cannot process input signals near the power rails, and hence the problem that the input voltage range is narrow.